Embodiments relate to a semiconductor device and a method of manufacturing the same. Some embodiments relate to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same.
A MOS Field Effect Transistor (MOSFET) may have relatively high input impedance compared to a bipolar transistor, providing an electrical benefit and/or a relatively simple gate driving circuit. A MOSFET may be a unipolar device having substantially no-time delay which may result from minority carrier storage and/or recombination while being turned off A MOSFET may be applied, for example, to switching mode power supply devices, lamp ballasts and/or motor driving circuits. A DMOSFET (Double Diffused MOSFET) may use planar diffusion technology.
A LDMOS transistor is described in U.S. Pat. No. 4,300,150 to Colak. A LDMOS device may be applied to a VLSI process due to its relatively simple structure. LDMOS devices may have minimized technical features than, for example, DMOS (VDMOS) devices. However, Reduced Surface Field (RESURF) SLMOS devices may have maximized on-resistance (Rsp). FIG. 1 is a sectional view illustrating a LDMOS device.
Referring to FIG. 1, high voltage well (HVWELL) 20 may be formed on and/or over p-type epilayer 10 which may be formed on and/or over a substrate. P-type body 30 may be formed on and/or over HVWELL 20. P+ region 74 and/or N+ source 70 may be formed on and/or over a surface of p-type body 30. N+ well 50 for Low Voltage (LV) may be formed adjacent isolation layer 40, and/or N+ drain 72 may be formed on and/or over N+ well 50. Gate dielectric layer 60 and/or gate electrode 62 may be partially overlapped with both a top of isolation layer 40 and source 70. Isolation layer 40 may be provided between drain 72 and source 70 to prevent an electric field from being concentrated on and/or over a region near a gate edge in a High Voltage (HV) device capable of outputting higher than approximately 30 V. Gate poly 62 may be lifted to use isolation layer 40 as a plate.
Electric currents may flow along a surface of a LDMOS device, which may minimize electric current driving efficiency. As shown in FIG. 1, when applying a relatively high voltage, an electric field may be concentrated on and/or over a region adjacent to a gate edge. To address electric filed concentration, a region near the gate edge may be corner-rounded but may be limited. As a result, a problematic disadvantage of device reliability and/or deterioration may occur.
Accordingly, there is a need for a LDMOS device and a method of manufacturing a LDMOS device that may minimize on-resistance and/or may acquire a relatively high breakdown voltage.